With the development of the semiconductor integrated circuit (IC) technology, the critical dimension of semiconductor devices also continuously becomes smaller. For conventional metal-oxide-semiconductor (MOS) field-effect transistors (FET), such a small critical dimension may lead to the short-channel effect as well as other disadvantages. With a relatively large channel, Fin-FET may overcome the short-channel effect and, thus, has been widely used. However, for Fin-FET with a fin structure made of Si, when the critical dimension shrinks to approach 16 nm, the carrier mobility in the channel may be low due to low mobility of electrons in Si, leading to a relatively small drive current and high energy consumption for the Fin-FET. Therefore, a material with higher electron mobility may be required to replace Si for fabricating the fin structure.
Certain technology is developed to use a Fin-FET with the fin structure made of III-V group elements (such as InGaAs). Because of the low energy consumption characteristics, the III-V group elements provide higher carrier mobility. However, when the critical dimension further decreases to 7 nm or even 5 nm, lower energy consumption of the Fin-FET may be required.
The Fin-FET can also have the fin structure made of InGaAs and covered by an InP layer. Because the lattice mismatch between the InP layer and InGaAs is small while the electron saturation velocity is high, the Fin-FET may demonstrate characteristics of low energy consumption. However, due to the limitation of process conditions, an InP layer formed by existing methods is usually thick. A thick InP layer may not be good for heat dispersion. In addition, such a thick InP layer may also require a relatively large drive voltage. Therefore, the InP layer may need to be thinned down to approach a thickness equal to or less than 1 nm.
Currently, a method for thinning down the InP layer often includes performing an ashing process on the InP layer using oxygen gas and then performing a wet etching process at room temperature to remove the ashed portion of the InP layer. An etch solution mixed by diluted sulfuric acid and water at a 1:1 ratio may be used during the wet etching process.
However, the wet etching process may introduce some contaminants, which may affect the performance of the device. In addition, as the device may need to be alternatively handled in dry and wet operation environments, the fabrication process may be more complicated, the processing time may be longer, and the probability of getting the device contaminated may also increase.
The disclosed fabrication methods and 3D transistors are directed to solve one or more problems set forth above and other problems in the art.